RELY - Design for RELIABILITY of SoCs for Applications like Transportation, Medical, and Industrial Automation
As the shrinking dimensions of SoCs make them increasingly prone to failure, methods are required to determine their reliability. At the same time SoC complexity is rapidly increasing due to integration of new functions, devices, sensors/monitors, extended operating conditions and package interactions. So new failure mechanisms will appear and system failures will increase due to higher device count and more interaction.
This project's goal is to ensure system reliability by means of design for future complex SoCs as they are needed in applications of high reliability like transportation, medical, and industrial automation.
The partners will address the issue in a straightforward and exhaustive way: starting from the description of key electronic components, which are candidates for SoCs, the partners will decompose them in subparts that will be integrated in different technologies, in order to cover as many components as possible as SoC implementation. This includes, but is not be limited to, logic functions in 65nm technologies and below, high temperature functions in 0.35µm technologies and actuator components. The consortium is composed to such combine a broad expertise in the relevant fields. For simplicity and cost reasons, the proof of concept will be demonstrated on the separate functions.
The consortium members are convinced that reliability must be addressed already in the design phase of the product. Hence, their efforts will focus on improving design rules to take reliability requirements into account on all design levels from the system and architecture level down to gate and transistor level. Moreover, the consortium will extend its "design-for-reliability" efforts to test coverage, and monitoring of functions and components. RELY will demonstrate that this unique combination of different solutions is necessary to fulfill the reliability requirements given the shrinking dimensions and increasing complexity of SoCs.
On May 1st 2011, the project started on a European level.